Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Configuration bitstreams have grown larger with each new generation of programmable ICs. The number of memory cells and amount of logic circuitry implemented on a chip or in an IC package continues to grow, allowing larger circuit designs, which require larger configuration bitstreams.
Large configuration bitstreams may be problematic. In order to reduce the time to boot a programmable IC, a configuration bistream can be stored on-chip or within the same package as the programmable logic circuitry, thereby reducing the time needed for configuration circuitry to retrieve the bitstream. However, providing on-chip or in-package storage for the configuration bitstream may require a large memory device and enlarge the footprint and cost of the device. Alternatively, a configuration bitstream can be stored off-chip or off-package to reduce device storage requirements. However, loading a large configuration bitstream from an external source may increase the boot time to an unacceptable duration.